The present invention is related in general to the field of semiconductor devices and processes and more specifically to thermally enhanced configurations of ball grid array and chip scale packages and to a method of fabricating these configurations using thin thermally conductive foils.
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore""s xe2x80x9clawxe2x80x9d), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
While plastic ball grid array (BGA) and chip-scale packages (CSP) became very popular in the last few years, they have been limited to fully participate in the trends for Moore""s law due to a number of shortcomings. It turned out to be difficult to reduce the cost of BGAs and CSPs due to high content of plastic materials and the fixed number of fabrication process steps. The reliability of plastic BGAs and CSPs suffers from sensitivity to thermo-mechanical stress and moisture absorption. Their thermal performance remains quite limited. It is difficult to adjust the package designs to custom requirements; consequently, the package designs are not flexible enough to fit the general application trends towards smaller package outlines and thinner profiles.
Known technology focuses the attention for developing BGA and CSP package designs and processes on devices with high lead counts (or solder ball numbers) and neglects the specific needs of BGAs and CSPs for smaller lead (or solder ball) numbers. Thus, opportunities in the huge application market requiring specifically low solder ball numbers go unattended.
In the present state of the art, plastic packages with small pin count use stamped or etched leadframes; these leadframes represent the dominant materials cost in these packages. Plastic BGAs and CSPs use patterned polyimide films as substrates for mounting the semiconductor chips; these films represent the dominant materials cost in these packages. Furthermore, as a consequence of these plastic films, the thermal performance of the packages is restricted.
According to the present invention for semiconductor integrated circuit (IC) devices, the molding process for encapsulating a chip mounted on a thermally conductive foil, is used to form configurations of the foil such that it is suitable for thermal contact and thus for dissipating thermal energy from the chip. Furthermore, according to the present invention, the molding process for encapsulating a chip mounted on a sheet-like insulating substrate having metal layers on one or both surfaces, is used to form configurations of the substrate such that it is suitable both for thermal contact and for electrical potential.
The present invention is related to high density ICs, especially those having low or modest numbers of inputs/outputs or bonding pads, further to devices using an electrically conductive or metallic substrate, to which they are usually connected by wire bonding, and also to devices requiring small package outlines and low profiles. These ICs can be found in many semiconductor device families such as processors, digital and analog devices, mixed signal and standard linear and logic products, telephone, RF and telecommunications devices, intelligent power devices, and both large and small area chip categories. The invention helps to insure built-in quality and reliability in applications such as cellular communications, pagers, hard disk drives, laptop computers, and medical instrumentation.
The invention provides some material and substrate design modifications and several simplifications of basic process steps commonly practiced in semiconductor assembly and packaging technology so that a significant manufacturing cost reductions are achieved. The chips are mounted on substrates provided as thin foils in the thickness range of about 10 to 75 xcexcm. In this thickness range, the foils responds to the molding pressure during conventional transfer molding processes, move against the steel surfaces of the mold cavity and align smoothly to the surface contours. The chip mounted on exposed foil areas is positioned during the molding operation such that it can create a path for dissipating thermal energy from the chip and can thus be used to best advantage in solder attachments. With the same ease, dimples reaching into the molded material and covered with a solderable surface can be created together with the exposed chip mount areas. The amount of elongation by which certain foil materials can stretch in order to move from their original flat configuration to a curved configuration, has been determined by this invention. Protrusions or indentions of the chip-mount area and ball-simulating elevations can be created between about 150 and 230 xcexcm high using an annealed copper foil of about 30 to 40 xcexcm thickness.
It is an aspect of the present invention to be applicable to a variety of different BGA and chip-scale packages, especially those for high power dissipation and with a xe2x80x9cballxe2x80x9d count of about 4 to 80.
It is another aspect of the present invention to be applicable to an assembly of active IC chips and passive electronic components, attached to a substrate designed to provide both transmission of thermal energy and application of an electrical potential.
Another aspect of the present invention is to introduce manufacturing steps which contribute to the trends towards packages with lower overall profiles and smaller outlines, thus contributing to device space conservation.
Another aspect of the present invention is to enhance the package reliability by improving the adhesion between the molding compound and the metal foil used for thermal and electrical contact to the outside world.
Another aspect of the present invention is to introduce manufacturing steps which contribute to the trends towards packages with lower overall profiles and smaller outlines, thus contributing to device space conservation.
Another aspect of the present invention is to improve product quality by process simplification, and to enhance reliability assurance by enhancing thermal energy dissipation, controlling thermomechanical stress, minimizing moisture absorption, and general in-process control at no extra cost.
Another aspect of the present invention is to introduce assembly concepts for thin profile packages which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several future generations of products.
These aspects have been achieved by the teachings of the invention concerning methods suitable for mass production. Various modifications have been successfully employed to satisfy different selections of product geometries and materials.
In one embodiment of the present invention, the size of the exposure of the chip-mount area and thus the stretch of the foil material necessary to achieve this exposure is used to produce devices of low profiles and improved power handling.
In another embodiment of the invention, the thermally improved product characteristics are combined with the capability of applying electrical RF ground potential, thus opening a new way of simplified production and a wide field of product application.
In another embodiment of the invention, the exposure of chip mount areas is combined with a number of depressions and the arrangement in rows of solder ball receptors on order to produce devices of small BGA and CSP outlines and assemblies thereof.
In another embodiment of the invention, the exposure of chip mount areas is combined with a number of elevations and the arrangement in rows of simulated xe2x80x9cballsxe2x80x9d in order to produce devices of small BGA and CSP outlines and assemblies thereof.
In another embodiment of the invention, the shape of the electrically conductive foil carrying a fixed electrical potential such as RF ground is designed so that this potential shields a pre-determined area of an electronic assembly.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.